Senior Front End Design Engineer (Microarchitecture) - Sunnyvale HQ

What this role involves

Cerebras Systems is hiring a Senior Front End Design Engineer to work on the Wafer Scale Engine, focusing on RTL design and integration. The role requires 8+ years of experience and deep expertise in high-performance, power-efficient chip design. The position is based in Sunnyvale, CA with a hybrid work environment and a salary range of $250,000 to $300,000.

Skills this posting asks for

• rtl design
• rtl integration
• synthesis
• functional specification
• micro-architecture
• python
• tcl
• tcp/ip
• rdma
• ethernet
• pcie
• cpu interfaces
• serdes
• fpga development
• place and route
• floor planning
• timing analysis
• asic vendor management

Requirements

• 8 years of experience
• Level: senior
• Remote policy: hybrid

From the employer’s posting

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transf…